Devices that contain microelectronic components generally require a transfer of information from the chip to one or several other components on the system. In many cases, these other components are not monolithically fabricated on the same chip, where they could be easily interconnected through a variety of techniques. Instead, a highly conductive layer sandwiched between two components is required to transfer information. One of the industry standard ways to do this it by flip-chip bump bonding. This technique requires the deposition of a soft conductive material to be deposited on either one or both of the microchips to be bonded. Once performed, the two components are optically aligned in a piece of equipment called a hybrid bump bonder, or hybridizer. After this alignment process, the two chips are pressed together by the hybridizer. This pressure, sometimes with the addition of heat, causes a permanent bond of the two components due to adhesion of the soft conductive layer.
Like most things in the microelectronics industry, the pitch of these flip-chip interconnects has gotten smaller over time. This small pitch makes it increasingly difficult to hybridize two chips with a high yield of successful bonds. In some cases, new technology has emerged that allows for small pitch interconnection through vastly different techniques. However, for a variety of reasons, these techniques are generally not suitable when bonding together chips that are composed of different substrate materials. One example of this is in the infrared sensing industry, where the light sensing focal planar array composed of HgCdTe grown on CdZnTe is hybridized to a read-out integrated circuit composed of Si. These devices are generally thermally cycled between room temperature when they turned off to 77° K during operation. A large difference in the thermal coefficient of expansion between CdZnTe and Si causes the two microchips to expand and contract differently over this temperature range. This places a requirement on the interconnects to be soft and relatively tall in order to conform to the stress caused by thermal cycling. Due to these requirements, indium is the preferred interconnect material. As higher resolution focal planar arrays with smaller pixels are produced, smaller pitch. In interconnects will be required to transfer information to the read-out integrated circuit. As this pitch falls below 10 μm, current technology will become less capable of successfully hybridizing the two microchips.